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83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 1 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer g eneral d escription the ics83026i is a low skew, 1-to-2 differ- ential-to-lvcmos/lvttl f anout buffer and a member of the hipercloc ks? f amily of high performance clock solutions from ics.the differential input can accept most differential sig- nal types (lvds, lvhstl, lvpecl, sstl, and hcsl) and translate to two single-ended lvcmos/lvttl outputs with a maximum output skew of 20ps. the small 8-lead soic foot- print makes this device ideal for use in applications with lim- ited board space. f eatures ? 2 lvcmos / lvttl outputs ? differential clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency: 350mhz (typical) ? output skew: 20ps (maximum) ? part-to-part skew: 600ps (maximum) ? small 8 lead soic package saves board space ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? lead-free package available ? pin-to-pin compatible with mc100ept26 b lock d iagram p in a ssignment ics83026i 8-lead soic 3.8mm x 4.8mm, x 1.47mm package body m package top view nc clk nclk nc 1 2 3 4 q0 q1 clk nclk hiperclocks? ics v dd q0 q1 gnd 8 7 6 5
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 2 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v 6 . 3 =3 2f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? r t u o e c n a d e p m i t u p t u o572 1 ? r e b m u ne m a ne p y tn o i t p i r c s e d 4 , 1c nd e s u n u. t c e n n o c o n 2k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 3k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 5d n gr e w o p. d n u o r g y l p p u s r e w o p 61 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e l g n i s 70 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e l g n i s 8v d d r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 3 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v0.3v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s r e w o p 0 . 33 . 36 . 3v i d d t n e r r u c y l p p u s r e w o p 5 3a m t able 3b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v0.3v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t d d . t i u c r i c t s e t d a o l t u p t u o v 3 . 3 , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / t able 3c. d ifferential dc c haracteristics , v dd = 3.3v0.3v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv n i v = d d v 6 . 3 =5a k l cv n i v = d d v 6 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv n i v , v 0 = d d v 6 . 3 =0 5 1 -a k l cv n i v , v 0 = d d v 6 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t d d . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i . a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 4 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t able 4. ac c haracteristics , v dd = 3.3v0.3v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 3z h m t d p 1 e t o n , y a l e d n o i t a g a p o r p? z h m 0 5 37 . 11 . 25 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 50 2s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 6s p t r t / f e m i t l l a f / e s i r t u p t u ov 2 o t v 8 . 00 5 10 0 30 5 4s p c d oe l c y c y t u d t u p t u o 0 40 50 6% f t a d e r u s a e m s r e t e m a r a p l l a x a m . n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . e s i w r e h t o d e t o n s s e l n u v t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n d d . 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m d d . 2 / s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a v t a d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 5 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer p arameter m easurement i nformation d ifferential i nput l evel 3.3vc ore /3.3v o utput l oad ac t est c ircuit scope qx lvcmos 1.65v0.15v -1.65v0.15v o utput s kew p art - to -p art s kew v cmr cross points v pp gnd clk nclk v dd t sk(o) v ddo 2 v ddo 2 qy qx t sk(pp) v ddo 2 v ddo 2 qy qx pa rt 1 pa rt 2 v dd gnd p ropagation d elay q0, q1 o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f t pd v ddo 2 clk nclk o utput d uty c ycle /p ulse w idth /p eriod pulse width t period t pw t period odc = v ddo 2 q0, q1
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 6 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 7 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 2a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 8 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t ransistor c ount the transistor count for ics83026i is: 416 t able 5. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. r eliability i nformation
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 9 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t able 6. p ackage d imensions reference document: jedec publication 95, ms-012 p ackage o utline - s uffix m for 8 l ead soic l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 10 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t able 7. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t i m a 6 2 0 3 8 s c ii m a 6 2 0 3 8c i o s d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t i m a 6 2 0 3 8 s c ii m a 6 2 0 3 8l e e r d n a e p a t n o c i o s d a e l 80 0 5 2c 5 8 o t c 0 4 - f l i m a 6 2 0 3 8 s c il i a 6 2 0 3 8c i o s " e e r f - d a e l " d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t f l i m a 6 2 0 3 8 s c il i a 6 2 0 3 8 n o c i o s " e e r f - d a e l " d a e l 8 l e e r d n a e p a t 0 0 5 2c 5 8 o t c 0 4 - the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.
83026ami www.icst.com/products/hiperclocks.html rev. b november 9, 2004 11 integrated circuit systems, inc. ics83026i l ow s kew , 1- to -2 d ifferential - to -lvcmos/lvttl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 . n o i t p i r c s e d l a r e n e g d e s i v e r 2 0 / 9 / 8 b 2 t 7 t 1 2 7 - 6 1 1 . n o i t c e s s e r u t a e f o t t e l l u b e e r f - d a e l d e d d a c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i l a c i p y t f p 4 o t . x a m f p 4 m o r f 5 d e d d a d n a ? 2 1 & . n i m ? o t . x a mr t u o . w o r . n o i t c e s n o i t a m r o f n i n o i t a c i l p p a d e d d a . e l b a t n o i t a m r o f n i g n i r e d r o o t n / p e e r f - d a e l d e d d a 4 0 / 9 / 1 1

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